Henderson, NV – May 15, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, is celebrating its 35th Anniversary at the 2019 Design Automation Conference (DAC), June 2-6, Las Vegas, NV, Las Vegas Convention Center and has prepared technical presentations aligned with many of the industry’s hottest topics.
“This year’s DAC is a very special one for us as it’s our 35th anniversary and is in Las Vegas, our home city,” says Zibi Zalewski, General Manager of Aldec’s Hardware Division. “During the conference our engineering team will be presenting the latest solutions for a complete verification flow, including multi-language, mixed-signal simulation and hardware emulation and multi-FPGA prototyping. Our technology experts will also be showcasing our latest embedded solutions for 4k video processing and DNN-based object classification using the latest FPGA platforms.”
The following presentations will be offered continuously throughout the three main days of DAC – June 3, 4 and 5 - at Aldec’s booth (#623)
Each presentation will last about 30 minutes and interested parties are advised to pre-register to select their preferred subject matter and to secure their preferred date and time slot; where presentation start times commence at 10:00 AM and end at 5:30 PM.
Also, all who attend a presentation will automatically be entered into a prize draw, as Aldec is giving away an Apple product on each of the show’s main three days. The prizes and their corresponding draw days are: an Apple iPad, on June 3; an Apple Smart Watch, on June 4; and an Apple MacBook Air, on June 5. Each day’s winner will be drawn at 5:00 PM.
4K Video Processing Embedded System Design by the Example of Optical Flow Read more
Image data resolution is constantly growing in different applications and 4K UltraHD resolution is a standard nowadays. We will demonstrate that Aldec TySOM board which based on Xilinx Zynq FPGA can be successfully used in application and FPGA chip can accelerate functions and algorithms to achieve high performance.
AI on The Edge - DNN Based Object Classification on TySOM EDK Read more
Object detection by a Neural Network is a hot topic nowadays in many fields such as automotive or industrial. Accurate and fast detection and classification is required. These requirements can be fulfilled with system based on FPGA accelerated SoC chips such as Xilinx Zynq. In this presentation we will demonstrate how to utilize Aldec TySOM board for object detection and recognition application.
Hybrid Co-Emulation with ARM Hardware Model Read more
Hardware-Software co-design and co-verification are indispensable in any kind of SoC design today. Fast and accurate hybrid emulation platform can be built using ARM Hardware Model provided by Xilinx Zynq MPSoC. We will demonstrate how to connect Xilinx Zynq MPSoC and its ARM Cortex A53/R5 processors with the largest Xilinx UltraSCALE US440 FPGA on HES emulation board.
Partitioning Design for Multi-FPGA Prototyping Read more
Multi-FPGA partitioning has always been a challenge due to limited number of FPGA I/Os and FPGA-specific clocking tree. Aldec provides HES-DVM Prototyping toolbox that automates design partitioning for multiple FPGAs and integrates ultra-fast HES Proto-AXI host bridge. This year we will demonstrate the new features and improvements that include: Automatic Partitions, Connections, Routing and third-party FPGA boards support.
Aldec and Silvaco Mixed-Signal Simulation Read more
Aldec and Silvaco continue their efforts to provide robust mixed-signal solution based on high-performance tools such as Riviera-PRO Advanced Verification Platform and SmartSpice Parallel SPICE Circuit Simulator. The demo will show mixed-signal simulation and debug capabilities. We will show how the digital and analog domains can communicate and how user can obtain results of Verilog-AMS and Verilog-D co-simulation in Riviera-PRO user interface. Users can view the co-simulation results using Riviera-PRO Advanced Waveform Viewer and debug using Riviera-PRO debugging features such as X-trace, Advanced Data-flow, Code Coverage Collector.
SoC Simulation Environment for Mixed-Signal Designs Read more
(1) Today's FPGA SoC embedded designs present new verification challenges for both software and hardware engineers. Aldec provides a HW/SW co-simulation approach based on open-source QEMU that can be run together with Verilog-AMS Slivaco SmartSpice co-simulation. Demo will show how to prepare and simulate pulse-width modulation (PWM) module with analog output. Simulation flow combines Riviera-PRO Advanced Verification Platform, Open-Source QEMU and SmartSpice Parallel SPICE.
(2) The world is analog in nature and since electronic devices often work relaying on data gathered by sensors, a system designer is commonly faced with the challenge of integrating digital and analog circuits into a single SoC. Therefore, the ability to efficiently simulate mixed-signal systems becomes essential. Aldec together with Silvaco provide a high-performance mixed-signal solution using Riviera-PRO Advanced Verification Platform and SmartSpice Parallel SPICE Circuit simulator. The demo will show simulation and debug capabilities for a smart sensor design. The design will include Verilog and Verilog-AMS modules as well as SPICE netlists and hardware emulation using open-source QEMU.
Register Generator for Design Register and Memory Management Read more
The increasing number of registers in complex designs becomes a challenge for modeling and verification. Any change in register definition should be automatically propagated to software and hardware engineers to reduce the costs and time involved. The Aldec Register Generator tool allows to create the RTL model for hardware designers, UVM model for verification engineers, C header for software designers and a memory map documentation for users. This presentation will show how to prepare an RTL register model, C definition header and HTML documentation from an IP-XACT or CSV description.
The world is analog in nature and since electronic devices often work relaying on data gathered by sensors, a system designer is commonly faced with the challange of integrating digital and analog circuits into a single SoC. Therefore the ability to efficiently simulate mixed-signal systems becomes essential. Aldec together with Silvaco provide a high-performance mixed-signal solution using Riviera-PRO Advanced Verification Platform and SmartSpice Parallel SPICE Circuit simulator. The demo will show simulation and debug capabilities for a smart sensor design. The design will include Verilog and Verilog-AMS modules as well as SPICE netlists and hardware emulation using open-source QEMU.
Advanced UVM tools in Riviera-PRO Read more
UVM is a very beneficial methodology when you are verifying large designs, but it also comes with added complexity. In this presentation we are going to take a look at various debug features and tools we have in Riviera-PRO that can make UVM code debug, a much easier process. We will take an in-depth dive into the UVM Toolbox, UVM Graph and other UVM features that will help navigate through the UVM environment and help with finding issues quickly and more efficiently.
Contact firstname.lastname@example.org or call +1(702)990-4400 for more details.
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community of more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives as well as researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area, with approximately 200 of the leading and emerging EDA, silicon, and intellectual property (IP) companies and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic System Design Alliance (ESDA), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM's Special Interest Group on Design. www.dac.com
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com