HES-MPF500-M2S150

Capacity

The board HES-MPF500-M2S150 includes one Microsemi PolarFire MPF500T FPGA logic module and one SmartFusion2 M2S150 SoC host module featuring ARM Cortex-M3. The board features a unique integration of a Microsemi SmartFusion2 SoC FPGA and PolarFire FPGA.

Available onboard external memory resources include DDR4 SODIMM slot and 2x 8Gb DDR3 memory (16Gb total). The board contains PCIe x4 interface switchable between FPGA and SoC modules and two QSFP+ connectors for high-bandwidth low-latency communications. The FMC connector compliant with ANSI/VITA 57.1 standard provides easy extensibility which can be used by Aldec FMC HPC connectors.

 

M2S150  MPF500T

Logic Elements (4LUT + DFF)

146K 481K

Math Blocks (18x18 MACC)

240 1480

Total RAM Mbits

4.488 33

Transceivers

16 24

I/O

574 584

 

Clocking

Clocking is provided by oscillators and PLLs. Dedicated oscillators are connected directly to the FPGA devices as well as onboard PLLs. The onboard PLLs provide any-frequency common clocks for both FPGA devices and dedicated any-frequency clocks to the MPF500T to accommodate a variety of applications. Clocking can also be provided through the FMC connector through thirteen (13) differential clock inputs to the MPF500T.

 

Hosting & Interfaces

The board is connected to a workstation or server through the board’s PCIe x4 edge connector. A wide variety of interfaces are available to be connected to the FPGA devices.

 

MPF500T PolarFire M2S150 SmartFusion2
  • DDR4 SODIMM
  • QSPI
  • QSFP+
  • FMC HPC (134IOs, 8Lanes)
  • USB <–> UART
  • USB – Device
  • USB <–> UART
  • ETH
  • QSFP+
  • 2x 8Gb DDR3
  • uSD
  • QSPI
  • 2x EEPROM (I2C)

Aldec provides HES.Proto-AXI software package with necessary documentation and design examples for the board. For quick bring-up of host connection, Aldec provides ready to use image of the embedded Linux for M2S150 device and standalone examples of peripheral usage in MPF500T device. Power is supplied by a standard 6-pin PCIe power cable.

fpga boards, fpga board, fpga development boardBLOCK DIAGRAM

HES-MPF500-M2S150

Devices Resources

  • FPGA1: PolarFire MPF500T-FCG1152
    • 481K Logic elements (4LUT + DFF)
    • 1480 Math Blocks (18x18 MAC)
    • 1520 LSRAM Blocks (20k bit)
    • 4440 uSRAM Blocks (64x12)
    • 33 Mbits Total RAM
    • 513 Kbits uPROM
    • 8 user DLL's, 8 user PLL's
  • FPGA0: SmartFusion2 M2S150-FC1152
    • Programming and control FPGA

Clocking

  • 2 user programmable PLLs - provide 6 global clocks to target FPGA, 4 global clocks to control FPGA and ref. clocks for SERDES and QSFP+ interfaces
  • 4 dedicated oscillators - 2 for each FPGA
  • CLK buffer for PCIe interface
  • 13 clock inputs and 2 ref. clk. for SERDES from FMC connector

Memory

  • Memories connected to the MPF500T
    • SODIMM – DDR4 connector
    • SPI Flash
  • Memories connected to the M2S150
    • 2x 8Gb DDR3 ECC
    • SPI Flash
    • 2x I2C EEPROM

High Speed Interfaces

  • Host interfaces connected to MPF500T
    • PCIe x4 Gen2 to control FPGA or target FPGA
    • QSFP+
  • Host interfaces connected to M2S150
    • PCIe x4 Gen2
    • Ethernet 1Gb
    • QSFP+
    • USB 2.0 Device

Power

  • Standard 6-pin PCI-EXPRESS power connector
  • Power supply voltages supervisors
  • Power Monitor (I2C)
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